5G Digital Beamforming SOC

The task will address the integrated circuits in 22FDX targeting the digital beamforming system in demonstrator 4. RF building blocks encapsulate Power Amplifier (PA) for the transmitter, Low-noise amplifier (LNA), RX/TX switches, RF variable gain amplifiers (VGA), and mixers, and tunable matching networks, which are required by low-power RF Front-End Modules. Analog and mixed-signal blocks encapsulate Analog-to-digital converters (ADC), digital-to-analog converters (DAC), IF filters, and clock generation circuitry and distribution for intermediary signal processing across the transceiver chain. There are several challenges in this field, to create low-power and low-noise clock generation circuitry, especially at mm-Wave frequencies and use digital techniques especially on 22FDX to provide the targeted performance. Also achieving high-bandwidth required for 5G systems is the main challenge to address by making the right trade-off and innovation in circuit design.
One of the major challenges of 5G MIMO systems is the large amount of generated data due to large number of transmit and receive channels. This task aims to address this challenge by investigating optimal parallel-serial and serial-parallel conversion techniques, as well as equalization and clock recovery at the receiving end.

Also, the task includes to derive IPs realized either as digital circuits (proven on silicon or FPGA platform) or as software library components accessible through an API (Application Programming Interface). The major challenge is the optimization at architectural level to minimize the power consumption with respect to the high data rates.

The phases of development include:

  • Architecture definition and specification
  • RTL code and/or algorithm development
  • Test and verification of the algorithm and/or RTL
  • Synthesis, place & route, and timing-closure if implemented as RTL
  • Validation of IP (either on silicon, FPGA, or embedded system) and documentation.